1. Field of the Invention
This invention relates to integrated circuit fabrication and more particularly to forming a high density multi-level metallization scheme employing localized interconnect formed prior to plug formation in order to provide routing between a pair of transistors located within a plane distal from the local interconnect.
2. Description of the Relevant Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed on the semiconductor topography and connected to contact areas thereon to form an integrated circuit. The entire process of making an ohmic contact to the contact areas and routing interconnect material between ohmic contacts is described generally as "metallization". While materials other than metals are often used, the term metallization is generic in its application. It is derived from the origins of interconnect technology, where metals were the first conductors used. As the complexity of integrated circuits has increased, the complexity of the metallization structure has also increased.
Building multi-level interconnect structures is well known in the art. Multi-level interconnect structures were developed as a result of the shrinkage of active devices combined with increased demands required to accommodate interconnect routed between the active devices. In many designs, the area required to route a level of interconnect exceeds the area occupied by the active devices. Multi-level interconnect technology has therefore gained in popularity. Interconnect dispersed across several elevational levels helps reduce the overall lateral area occupied by the interconnect--leading to an increase in integrated circuit packing density.
Local interconnects are a special form of interconnect. Local interconnects are relatively short routing structures, and can be made of numerous conductive elements. A popular local interconnect comprises doped polysilicon, or reacted polysilicon termed "polycide". In whatever form, local interconnect is beneficial to the formation of multi-level interconnect structures. Local interconnect can be used to provide coupling between a gate conductor of a MOS transistor and a source or drain implant region (hereinafter "junction") of that transistor. Such coupling effectuates a diode. Local interconnect has also been used to couple a gate conductor of one transistor and a source or drain junction of another transistor. This form of coupling is prevalent in all input-output connections of, for example, standard logic cells. FIGS. 1 and 2 illustrate an example of such a local interconnect.
The circuit diagram of FIG. 1 depicts a single input forwarded into a pair of gate conductors 10 of an inverter 11. The output of inverter 1 is shown, according to one example, fed into one of the two inputs of a NOR gate 12. Local interconnect 13 is used to effectuate the interconnection between inverter 11 and NOR gate 12 by locally connecting a drain junction 14 of inverter 11 output to a gate conductor 16 of NOR gate 12.
FIG. 2 depicts the circuit diagram of FIG. 1 using logic symbols. Inverter 11 and NOR gate 12 are shown in symbolic form. FIG. 2 further demonstrates that local interconnect 13 output from inverter 11 may also be connected to a second gate conductor via possibly an extension 13a to local interconnect 13. Extension 13a can therefore route to a gate conductor of a second NOR gate 22.
The formation of a local interconnect between a gate conductor of one transistor of, for example, NOR gate 12 and a junction of another transistor of, for example, inverter 11 generally involves a plug. A plug is defined as a structure extending between conductive planes dielectrically spaced from one another. A plug can be formed by forming an opening through an insulative layer and thereafter filling the opening with a conductive plug material. The conductive plug material extends through the insulative (dielectric) layer disposed upon the two transistors and the single-crystalline substrate on which the transistors reside upon and partially within. A first plug extends through the dielectric to the gate conductor of one transistor while another plug, laterally spaced from the first plug, extends to a junction of another transistor. A conductive layer, i.e., a local interconnect, which contacts the upper surfaces of the two plugs is then formed horizontally above the dielectric layer. The local interconnect therefore extends from above one plug to an area above the other plug. The plugs serve as intermediaries between the overlying interconnect and the underlying gate conductor and underlying junction.
A problem with the above-mentioned method for the formation of such a local interconnect is that the plugs occupy one level of the multi-level integrated circuit while the local interconnect occupies another level. The local interconnect occupies space which could better be used for additional routing of distally extending interconnect, such interconnect defined as routing runs which extend across, for example, the entire or a substantial portion of the integrated circuit die. By placing the local interconnect in a plane common to distally extending interconnect, the area available to the distal interconnect is limited. Thus, the packing density of the integrated circuit is somewhat sacrificed by the local interconnect and associated plugs. Moreover, no means is provided for other interconnect structures to communicate with the local interconnect. Packing density around the local interconnect is then further limited. These limitations on density prevent an increase in circuit speed as well as an increase in circuit complexity. It is therefore desirable that a semiconductor fabrication process be developed for the formation of a local interconnect which allows for higher density layout of advanced ULSI integrated circuits containing local interconnect.